1. Field of the Invention
The invention relates to a circuit for controlling writing data to a memory, and more particularly to such a circuit to be used for a micro-computer storing a memory therein.
2. Description of the Related Art
A circuit for controlling writing data to a memory has been used for preventing data to be written into a memory from being destroyed and further for protecting the data when a reset factor is generated while the data is being written into a memory. One of such circuits has been suggested in Japanese Unexamined Patent Publication No. 63-208958.
FIG. 1 is a block diagram illustrating a structure of a conventional circuit for controlling writing data to a memory. A central processing unit (hereinafter, referred to simply as "CPU") 95 transmits a data signal 90 and a memory reading signal 91 to a memory 96. CPU 95 transmits a memory writing signal 92 to a memory control signal control section 97 while data is being written into the memory 96, and the control section 97, on receiving the memory writing signals 92, determines whether transmittance of signals to the memory 96 is allowed or inhibited. A section 98 judges whether data is now being written into or being read from the memory 96, and stops transmission of reset-allowing signals 99 to a reset signal generator 100 while data is actually being written into or being read from the memory 96. The reset signal generator 100, when a reset factor is generated, would transmit a reset signal 94, if the reset-allowing signal 99 were in allowed condition. If the reset-allowing signal 99 is in inhibited condition, the reset signal generator 100 would not transmit the reset signals 94 until the reset-allowing signal 99 enters allowed condition.
The illustrated circuit operates as follows. FIG. 2 illustrates wave-forms of the signals 92, 99 and 94. If a reset factor is not generated, the reset signal 94 is not transmitted in the circuit illustrated in FIG. 1, and hence data is able to be always written into the memory 96. If the time T.sub.R at which a reset factor has been generated is within a period when CPU 95 is writing data into the memory 96, since the memory writing signal 92 is valid, the section 98 causes the reset-allowing signal 99 to have an inhibition value in order to prevent production of the reset signals 94. Suppose that CPU 95 has completed writing data into the memory 96 at the time Ts while the reset signals 94 are prevented from being produced. Since the memory-writing signal 92 is invalidated, the section 98 causes the reset-allowing signal 99 to have an allowance value. As a result, the reset signal 94, which has been prevented from being produced, is produced, and thus, reset of the circuit is carried out. Thus, a reset does not take place while data is being written into the memory, and hence a period of time necessary for data to be written into the memory is guaranteed, and it is made sure that no error data is written into the memory.
However, the above mentioned conventional circuit has a problem as follows. If the reset signal 94 produced in the circuit illustrated in FIG. 1 is used as a reset signal for CPU 95 or other circuits, timing at which reset is carried out is different between a case where an external reset factor overlaps the memory-writing signal and a case where an external reset factor does not overlap the memory-writing signal. Accordingly, a system including a micro-computer having the above mentioned circuit for controlling writing data into a memory may induce malfunction.
The reason is that there is a possibility that a period of time where only a micro-computer is not reset may occur in a system including a micro-computer having the above mentioned conventional circuit.
A typical example thereof is described hereinbelow. In general, a period of time necessary for a non-volatile memory to write data thereinto is quite longer than that of DRAM and SRAM. Specifically, it takes tens of .mu. sec or longer for writing data into a non-volatile memory. In a circuit system employing a general semiconductor integrated circuit, a reset duration is in the range of 10 .mu. sec to tens of .mu. sec at minimum, though a reset duration depends on an operation frequency of the circuit. When such a memory is used, a valid reset duration transmitted from outside may be shorter than a period of time for writing. Hence, it may occur depending on the overlapping timing that an external reset signal is input while data is being written into a memory, and the external reset signal is determined valid, and that writing is not completed yet when the external reset signal is invalidated after a certain valid duration has passed. Hence, there exists a period of time in which a micro-computer is not reset, even after a valid reset duration has passed.